library ieee;
use ieee.std_logic_1164.all;
entity raminst is
port(
adr_i: in bit_vector(3 downto 1);
data_out: out bit_vector(15 downto 0)
);
end raminst;
architecture BBB of raminst is
begin
p0: process (adr_i)
begin
case adr_i is
when "000"=>data_out<="0100000100010010";
when "001"=>data_out<="0100001000001110";
when "010"=>data_out<="1010011010000000";
when "011"=>data_out<="1000001011000000";
when others=>data_out<="0000000000000000";
end case;
end process;
end ;