library ieee;
use ieee.std_logic_1164.all;
entity reg8 is
port(
data_i: in std_logic_vector(7 downto 0);
clk_i: in std_logic;
ena : in std_logic;
ctrl : in std_logic;
data_out: out std_logic_vector(7 downto 0)
);
end reg8;
architecture arch of reg8 is
signal regist: std_logic_vector(7 downto 0);
begin
process (clk_i)
begin
if(rising_edge(clk_i)) then
if(ena ='1') then
regist <= data_i;
end if;
end if;
end process;
data_out <= regist when ctrl = '1' else "ZZZZZZZZ";
end arch;